The present invention relates to a polynomial vector arithmetic operation control system in a data processor.
A conventional arithmetic operation control system in a vector arithmetic processor under the control of a central processing unit (to be referred to as a CPU hereinafter) has a system configuration shown in FIG. 1.
The vector arithmetic processor includes one instruction code register 11, an instruction decoder 15 addressed by an instruction code set in the instruction code register 11, an instruction execution start command register 16 for generating a command representing the start of instruction execution of the vector arithmetic processor, an arithmetic control unit 17, and an arithmetic unit 18. The instruction is defined as a minimum unit of arithmetic operation executed by the vector arithmetic processor and is exemplified by an addition, a subtraction, a multiplication, and the like. The instruction is defined as an instruction code of a few bits. Information representing how the vector arithmetic processor is operated on the basis of the instruction code is recorded in the instruction decoder 15.
When a CPU (not shown) sets an instruction code in the instruction code register 11, the instruction execution start command register 16 is set. The instruction code is supplied to the instruction decoder 15 through a line 102 and is decoded thereby. The instruction decoder 15 sends a signal for an arithmetic operation to the arithmetic control unit 17 in response to the input instruction code. At the same time, the instruction execution start command register 16 sends an instruction execution start command signal to the arithmetic control unit 17, thereby operating the arithmetic unit 18.
In the conventional arithmetic operation control system described above, only one instruction code register is used to directly address the instruction decoder 15. Accordingly, assume that one instruction (e.g., an addition) is repeatedly executed, this instruction is set in the instruction code register 11 once to repeat the corresponding arithmetic operation. However, if a polynomial vector arithmetic operation is performed wherein one result is obtained by using a plurality of instructions (e.g., a combination of multiplication and addition), the corresponding instruction codes must be alternately set in the instruction code register 11, resulting in inconvenience.